Keynote 2 – Western Digital
Data-centric Architecture
for the Zettabyte Age
Tuesday, August 6th, 11:40 am
Dr. Siva Sivaram
Siva Sivaram, Executive Vice President, Silicon Technology & Manufacturing
Western Digital
Dr. Siva Sivaram is Executive Vice President of Silicon Technology and Manufacturing for Western Digital, responsible for the company’s industry-leading NAND flash memories and other memory and storage technologies. Sivaram has more than 35 years of experience in semiconductor technology and manufacturing. He has held executive positions at Intel, Matrix Semiconductor and at SanDisk after its acquisition of Matrix. Additionally, he was the founder and CEO of Twin Creeks Technologies, a solar panel and equipment company. Sivaram serves on the board of directors of the Global Semiconductor Alliance and the US-India Business Council. He has been on the board member of several start-up firms and was entrepreneur-in-residence at Crosslink Capital and XSeed Capital. Sivaram received his doctorate and master’s degrees in materials science from the Rensselaer Polytechnic Institute where he has been elected to its Board of Trustees. Additionally, he is a Distinguished Alumnus of the National Institute of Technology, Tiruchi, India, where he received his bachelor’s degree in mechanical engineering. Sivaram has published numerous technical papers and a textbook on Chemical Vapor Deposition and holds several patents in semiconductor and solar technologies.
Christopher Bergey
Christopher Bergey, Senior Vice President, DevicesWestern Digital
Christopher Bergey is Senior Vice President of Devices Product Marketing and Management at Western Digital responsible for the Data Center, Client Compute, Embedded and Mobility product offerings. Bergey leads Western Digital’s devices product portfolio, from definition and strategy to concept and customer acceptance. Previously, Bergey was Vice President for Embedded and Integrated Systems (EIS) at Western Digital, focused on developing and driving product strategies in mobile and compute, as well as new markets including automotive, connected home, smart city and industrial IoT market segments. In this role, he led industry adoption of TLC (three-bits-per-cell) into the mobile market.
Prior to joining Western Digital in 2014, Bergey held multiple executive positions including VP of Marketing at Luxtera, VP of Mobile and Wireless at Broadcom, and Director of VLSI marketing at the Multilink Technology Corporation. Through this experience, Bergey has uniquely spent his career driving connectivity innovation in cloud datacenters as well as mobile and embedded markets.
Bergey holds a Bachelor of Science degree in Electrical Engineering from Drexel University and a Master of Business Administration in Finance and Economics from the University of Maryland. He is a frequent author and speaker on topics such as IoT, mobility, and the implementation of data-centric memories and architectures to address the Zettabyte Age.
Abstract:
In order to meet the explosive growth of data, flash memory manufacturers must continue to advance technology. The introduction of the charge trap memory cell helped enable fast and high-endurance SLC, brought TLC into the mainstream and is now leading to the introduction of QLC. However, the real potential of QLC and other forms of high-density storage such as Shingled Magnetic Recording (SMR) hard disk drives is not realized in today’s data center. A new, data-centric architecture is needed to address the growing complexity of workloads, applications and AI/IoT datasets. It must involve multiple tiers of purpose-built compute and storage, as well as new approaches to system software. Zoned-block storage allows data to be intelligently placed and sequenced. This enables lower TCO and optimizes the use of emerging high-density storage, without sacrificing performance. In the Zettabyte Age, architects need to explore innovative approaches to data center architecture to unlock the benefits of the next generation of storage.
Keynote 3: SK hynix
Subject:
4D NAND: The New Leader in Flash
Tuesday, August 6th, 1:50pm
Hongsok Choi
VP NAND Development/Design
SK hynix
Hongsok Choi is VP of NAND Development and Design, SK hynix. Over the 26 years of his career, Mr. Choi has designed and developed various SRAM, DRAM and 2D & 3D NAND flash products. Currently, his responsibility focuses on developing the next generation of 3D NAND. Mr. Choi holds an M.S. in Electric & Electronic Engineering from KAIST (Korea Advanced Institute of Science and Technology).
Andrew (Hyonil) Chong
SVP of NAND Solution Development
SK hynix
Andrew (Hyonil) Chong is Senior VP and Head of SK HMS Korea, where he is responsible for
the development of ASIC, FW and hardware for Mobile (eMMC, UFS, MCP) and SSD NAND
solution products. A 27-year veteran of the storage business including HDD, HBA, and SSD,
Mr. Chong has worked on developing SoC controllers at renowned companies such as
Cirrus Logic, LSI, and Marvell, as well as a startup. Mr. Chong holds a degree in Electrical Engineering and Computer Science from the University of California at Berkeley.
Abstract:
3D NAND has been very successful, but further advances are essential to meet the demands of cloud providers and new technologies such as 5G, AI, and IoT. One promising approach is to use charge trap flash (CTF) and periphery under cell (PUC) technologies to create a fourth dimension. It allows for significantly higher densities, thus reducing cost and maximizing value. In particular, it leads to a seamless transition to the next generation of flash technology that can replace conventional storage in many applications. 4D NAND solution in combination with the next generation high performance interfaces leads to major improvements in capacity, performance and reliability. Additionally, it will accelerate the adoption of NAND based storage considerably by offering new cost and performance levels.
Keynote 4: NGD Systems
Subject:
Computational Storage Helps Solve
Huge Analytics and ML Problems
Tuesday, August 6th, 2:20pm
Vladimir Alves
Co-Founder & CTO
NGD Systems
Vladimir Alves is co-founder/CTO at NGD Systems, where he focuses on developing SoCs that implement intelligent storage technology for data centers and fog computing. He has developed SoC-based solid state solutions for over 10 years, during which his teams have released many enterprise SSD controllers. Before co-founding NGD Systems, he was Sr Director of SSD SoC Development at Western Digital and STEC. He is the author of over 30 scientific publications on subjects including SoCs and computer architecture, and the co-author of over 20 patents. He earned his PhD in microelectronics from the National Polytechnic Institute of Grenoble, France.
Scott Shadley
VP Marketing
NGD Systems
Scott Shadley is VP Marketing at NGD Systems where he leads marketing, product management, and product development for the company’s industry-leading computational storage. He has been a key figure in promoting computational storage, being co-chair of the SNIA Technical Working Group on the subject which he helped found, and speaking on the subject at Open Compute Summit, Flash Memory Summit, NVMe Developer Days, and many other events, press interviews, blogs, and webinars. Before joining NGD Systems, Scott managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were multimillion dollar sellers. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
Abstract:
Everyone wants to get the greatest possible value from the enormous amounts of data they are now collecting. Not only does this require tremendous computing power, but it also requires easily scalable solutions that can handle even more data in the future. Computational storage is a key part of the answer. It brings compute to the edge where the data is stored. This both avoids the need to move large amounts of data around and reduces the strain on facilities such as central processors, networks, and other systems and devices. And scalability becomes simple! All you do is add more storage units (which you obviously need anyways), and the compute power increases automatically. A use case involving in-storage machine learning shows particularly promising results. It makes the training stage orders of magnitude faster than established learning models. Computational storage can thus meet the challenges of data analytics, AI/ML, and high-performance computing in edge, cloud, and hyperscale datacenters.
-Ohshima.jpg "Shigeo (Jeff) Ohshima, Technology Executive, SSD Application Engineering")
