Hongbin Zhu

Vice President of Research & Development

YMTC

Dr. Hongbin Zhu is the Vice President of Research & Development at YMTC, focusing on product process development. Dr. Zhu has over 20 years of experience in semiconductor process research and development, with expertise in process improvement and development, equipment and material development, and process integration.

Dr. Zhu received his Ph.D. in chemical engineering from the University of Arizona and holds more than 100 patents.

Abstract:
In the same way the universe is ever-expanding, so is the "DataCosm" - the unique confluence of data, storage and compute. With 5G and AI accelerating the DataCosm's virtuous growth cycle, optimized storage and industry partnership are critical to addressing high performance, continuous bit growth and cost. Innovations in NAND technology address these needs at scale, with multiple technologies and manufacturing to keep pace with the evolving DataCosm and customer's needs. Solidigm and SK hynix are on the leading edge of SSD and NAND innovation, enabling our partners to deliver on the promise of the DataCosm across industries and applications.

Abstract:
New and increasingly important data-centric workloads, such as real-time analytics, AI/ML, VR/AR, IoT, HPC, and cybersecurity, demand tremendous throughput at a reasonable price. The current memory/storage hierarchy of DRAM and flash cannot do the job alone. A new tier is needed that is persistent, high-throughput/low-latency, production-proven, low-cost, scalable, and simple to integrate into existing designs. Such a tier can provide a tremendous speed boost at an affordable cost. Use cases are already available for a wide variety of key applications, and results show major advances in speed, cost/performance ratio, power consumption, and scalability.

Abstract:
With the demand for workloads to scale up, down and everywhere in between, public cloud and hybrid cloud environments are under pressure to provide the ultimate in performance while at the same time remaining cost-competitive. Designing the highest performing storage and memory infrastructure for all workloads remains an expensive proposition at cloud scale, often resulting in underutilized resources - there has to be a better way. Optimizing NVMe and CXL-based silicon solutions from both a hardware and firmware perspective is proving the be the key to success in driving the foundation for the most scalable data center infrastructure.

Andy Hsu

CEO

NEO Semiconductor

Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company's growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master's degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor's degree from the National Cheng-Kung University in Taiwan.

Abstract:
CPUs and GPUs have made quantum leaps in computing speeds with acceleration of up to 60% every year. Yet, DRAM data latency improved about 30% over 20 years, while NAND flash became 3-5 time slower. The next wave of enterprise and consumer workloads will demand higher performance memory and storage solutions to better match computing speeds.

Architectural changes for memory and storage can overcome the limitations of conventional designs. The answer is in new architectures that can significantly reduce data latency while lowering power and improving throughput, respectively. We will explore visionary ways to design memory architectures and various innovative techniques that can fuel greater sustainability and accelerated performance for cloud and enterprise data centers while also enabling an entirely new generation of cost-effective consumer and mobile devices.

Pete Hazen

Vice President, Data Center Solutions

Microchip

Pete Hazen is Vice President of Data Center Solution business at Microchip (Nasdaq: MCHP). In this role, Pete is responsible for storage, memory and compute connectivity solutions as well as SSD controller solutions for next generation data centers. Pete is a 35-year industry veteran with experience in silicon design and architecture, applications engineering and marketing, business development, strategy and management. Pete holds a Bachelor of Science degree in Electrical Engineering from the University of Wisconsin-Madison. He holds over 20 patents in hardware and software.

Abstract:
Data centers continue to have the formidable task of gaining control of their IT investment spend by improving operating efficiency, reducing complexity, and increasing scale in the face of evolving and varied workload requirements. New architectures have emerged to better utilize and optimize hardware assets spanning across compute, storage, and now memory tiers. Resource agility is essential to unlocking efficiencies and eliminating stranded and underutilized assets. We will explore the innovations on the leading edge of these flexible architectures, examine primary barriers to adoption, and highlight technologies that both the industry and vendors like us have delivered.

Gary Adams

Senior Director of Marketing

Silicon Motion Inc.

Gary Adams is Senior Director of Marketing at Silicon Motion. He leads a focused team in defining and promoting Enterprise controllers and development platforms that accelerate high performance, data center SSD development. Gary has over 20 years in providing innovate leadership storage products and business solutions addressing market application needs. He has held various marketing and sales management positions at Microchip, Microsemi, PMC-Sierra and IDT. He earned a BSEE and MSEE at CSU-Chico.

Abstract:
Fueled by unprecedented technology growth, new innovation engines in chip design and SSD firmware architectures are required to address next generation data center optimizations maximizing performance and capacity while reducing power and TCO. New SSD design needs to address the litany of new form factors, security threats, NAND technology transitions to QLC and beyond while supporting evolving standards. To face these challenges at speed, new approaches are needed in providing firmware design flexibility and scalability enabling differentiation while reducing development time to market.

Debendra Das Sharma

Senior Fellow, Data Platforms and Artificial Intelligence Group

Intel

Dr. Debendra Das Sharma is an Intel Senior Fellow in the Data Platforms and Artificial Intelligence Group and Chief Architect of the I/O Technology and Standards at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture.

Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Das Sharma has a bachelor's in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He is a frequent keynote speaker in various conferences and a Distinguished Lecturer in leading Universities. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the Outstanding Engineer Award by IEEE Region 6 in 2021, and the Industrial Pioneer Award by IEEE Circuits and Systems in 2022.

Abstract:
The trends are undeniable, data growth is exploding, compute demands are unprecedented, system costs are increasing, and current data center infrastructure is under tremendous pressure. In order to address these challenges and unleash the full potential of data, Intel believes change begins at the underlying hardware architecture. This session will focus on Intel's efforts to drive disruption in the traditional memory-storage hierarchy and discuss the data-tiering evolution led by Optane technology. With the future always in mind, Intel has been building for the future of interconnected computing with the ecosystem. We will share our vision for delivering new CXL-enabled usages with Optane technology and how these new capabilities will deliver value to customers.

Matt Eastwood

Senior Vice President

IDC

Matt Eastwood is Senior Vice President of IDC's enterprise infrastructure, cloud, telecom, security, developers, channels and enabling technology research groups. Mr. Eastwood and his team research people, process and technology trends affecting the enterprise technology marketplace worldwide. Mr. Eastwood first joined IDC in 2000 as part of the server team and his responsibilities have evolved and expanded during his tenure. In his current role, he leads a team of more than 100 analysts providing insights and analysis to IT suppliers, buyers, investors, and distributors through more than 75 syndicated research programs. Mr. Eastwood also leads IDC's BuyerView primary research programs which are focused on defining emerging trends in cloud, developers, service providers, edge, AI and security.

Abstract:
The last few years have pressure tested digital infrastructures around the globe while forcing business leaders to rethink the foundational importance of infrastructure as they seek the scale, agility and efficiency necessary to be a digitally driven enterprise. As the industry looks forward, organizations will continue to leverage technology to underpin every process, prioritize key business initiatives, and stabilize their value chain as the journey to overcome the economic shock we are facing in 2022 and beyond. Attend this keynote session with analyst Matt Eastwood, Senior Vice President at IDC, who will discuss the challenges and opportunities facing today's infrastructure market given the changes to global dynamics and customer priorities.

Scott Baker

Chief Marketing Officer of IBM Hybrid Cloud Portfolio

IBM

Scott is a recognized technology leader with proven practical technology expertise, year after year proven success that drives innovation, creative and edgy marketing strategies, and a consistent focus on tactical execution to achieve business strategies. At IBM, he leads a product marketing team responsible for being the voice of IBM Servers, Storage and Technical Services products and solutions in the market and the voice of the market in the products. Since joining IBM, Scott's has revised our go-to-market strategies, brought the storage brand to the forefront of the pan-IBM marketing and digital efforts, and championed some of the more successful marketing launches that have been made to date. Over the past 25 years, Scott has held senior positions with major storage vendors, most recently as Vice President of Product Marketing for the Pure Storage FlashArray portfolio. Prior to that, Scott held leadership positions in product management, product marketing, product development and strategy at Hitachi Vantara, HPE / HP Inc., NetApp and EMC. Prior to joining the storage industry, Scott left a successful start-up, worked as Software Engineering Manager for the Nation Aeronautics and Space Administration and served in the US Army. Scott holds a Bachelor and Master of Science in Computer Science from Columbia Southern University and an MBA from the University of N. Alabama. In his spare time, Scott is an avid SCUBA diver, diving instructor and underwater photographer.

Abstract:
Storage continues to play a critical role as the "data custodian" in enterprise operations and cyber resiliency strategies. In addition to providing containers where data is stored when not in main memory or cache, the storage layer is also responsible for providing safeguarding functions that help organizations recover from unusual events. While most enterprise storage solutions on the market today focus on response and recovery operations, at IBM we believe the first step in creating an information supply chain that cannot be breached is to imbue the storage array with device-level threat intelligence. Join us in this session where we discuss the integration of AI/ML models into our FlashCoreModules as an added computation storage service explicitly designed to identify and detect threat signatures and initiate automated response operations to protect the organization and its data from unauthorized access and use.

Abstract:
Paul Saffo will lead a discussion with key representatives from the world's top flash memory manufacturers will discuss topics related to NAND Flash Memory, including key events over the last 35 years since its introduction, applications that wouldn't exist if NAND flash had not been invented, the new applications that NAND will be enabling, and the next challenges that are expected to continue innovation in NAND Flash and forms of memory.