Flash Memory Summit

2023 Keynotes Profiles and Abstracts

Keynote 1: KIOXIA
The Future of Flash Memory

Tuesday, August 8th, 11:00 am

Shigeo (Jeff) Ohshima, Technology Executive, SSD Application Engineering

Shigeo (Jeff) Ohshima

Technology Executive, SSD Application Engineering


Jeff Ohshima is a member of the technology executive team at KIOXIA America, where he focuses on SSD development and applications engineering. He was previously VP Memory Technology Executive at Toshiba America Electronic Components focused on flash memory with an emphasis on SSDs. He has also been Senior Manager R&D in the advanced NAND flash memory design department, responsible for 70 nm, 56 nm, 43 nm, and 32 nm part design. He has worked on memory at Toshiba for over 30 years, including 20 years on DRAM where he acted as a lead design for application specific memories and did technical marketing. Ohshima has served as a Visiting Research Scientist at Stanford University. He holds a BSEE and MSEE from Tokyo's Keio University.

From the invention of NAND flash memory in 1987 to today, flash has become integral to everyone's lives. The world continues to evolve, requiring innovation in flash memory technology to continuously stay ahead of the increasing demands for fast and reliable storage. KIOXIA continues to make investments in R&D and FABs to develop innovative new flash memory technologies and increasing capacity, helping to enable exciting new applications for the future. From BiCS FLASH™ 3D flash memory and chip packaging, to industry specifications and interfaces, to new applications and use cases, KIOXIA will present the latest innovations coming today and on the horizon. The future of flash memory.


Lifetime Achievement Awards

 Tuesday, August 8th, 11:30 am

Presented by:

Brian Berg

Brian Berg

Conference Technical Chair
& President

Berg Software Design

Chuck Sobey

Chuck Sobey

Conference Chair &
Chief Scientist


Jim Handy

Jim Handy

Sr Program Advisor &
Semiconductor Analyst

Objective Analysis

Flash Memory Summit's Lifetime Achievement Award (LAA) recognizes individuals who have shown outstanding leadership in promoting the development and use of flash memory and associated or related technologies, including creating or promoting an important non-volatile memory technology, leadership in the industry, and bringing flash technology to a new and important application. By bestowing this award, Flash Memory Summit hopes to help foster further advances in the fastest-growing technology of the semiconductor industry.

Keynote 2: Samsung
The Road to Flash Memory
Innovation in the AI Era

Tuesday, August 8th, 11:40 am

Dr. Luca Fasoli

Jinman Han

President of Samsung Device Solutions Americas

Samsung Electronics

Jinman Han serves as President of Samsung Device Solutions Americas (DSA) and Corporate EVP of Samsung Electronics, responsible for Samsung's U.S. semiconductor business, which includes Memory, Foundry, System LSI, and LED. Jinman is a respected leader who has held many leadership positions at Samsung throughout his career, most recently as head of the Memory Global Sales & Marketing team. He joined Samsung in 1989 and has worked in various departments, including DRAM design, Flash design, Flash solution product planning, Memory product planning and application engineering, and SSD development. His expertise and insight in the industry have contributed significantly to the company's presence within the memory market and have helped maintain Samsung's market leadership for decades. Jinman is based in San Jose, CA, and holds a bachelor's degree in Electrical Engineering from Seoul National University in Korea.

Khurram Ismail

Yong Ho Song

Corporate EVP, Solution Product R&D Division, Memory Business

Samsung Electronics

Yong Ho Song is a Corporate Executive Vice President of the Solution Product R&D Division in the Memory Business of Samsung Electronics. He is responsible for developing and delivering flash storage products ranging from UFS Mobile Memory Devices to Client - Server and Enterprise-class SSDs. Before his appointment as head of the Solution Product R&D Division in 2023, he led the controller development team. Yong had worked as a professor at Hanyang University since 2003 and performed many research projects on system architecture and software systems of memory-based storage systems resulting in an open source form, called Open SSD. Yong has published more than 150 technical papers in top academic journals and conferences and has served as a program committee member of many prestigious conferences, including the IEEE International Parallel and Distributed Processing Symposium, the IEEE International Conference on Parallel and Distributed Systems, the IEEE International Symposium on High-Performance Computer Architecture.

In line with the trend of customers' demanding higher storage performance, scalable multi-petabyte capacity coupled with creating an increasing amount of data, Samsung is focusing on developing innovative product solution that address these customer requirements. In the era of PCIe Gen5 and UFS 4.0, our first product solution has been successfully introduced to the market. In addition, the 8th generation of Vertical NAND has been successfully launched taking performance to incredible new levels. With the recent emergence of new innovative customer applications including AI and ChatGPT, it is fueling Samsung innovation for memory solutions to address the AI era such as Processing in Memory (PIM), Computational Storage with SmartSSD, and Memory Semantic SSD with MS-SSD. These memory solutions will play an important role in supporting IO performance for large data analytics models. We are leading the industry in open-source activities along with creating a platform to communicate and collaborate with customers through SMRC (Samsung Memory Research Center). We are excited about what the future will bring.

Keynote 3: SK hynix
Industry-Leading "4D" NAND Technology and
Solutions Enabling Multimodal AI Era

Tuesday, August 8th, 1:10pm

Hongbin Zhu

Jungdal Choi

Executive VP and Head of NAND Development

SK hynix

Jungdal Choi, EVP & Head of NAND Development, SK hynix Jungdal Choi, concurrently Head of NAND Development at SK hynix and NAND Engineering at Solidigm, is in charge of overseeing the 4D NAND development through the utilization of the 3D CTF design paired with the PUC (Periphery Under Cell) technology. He started his career in 1986 designing EEPROM circuits, and since then, he has been involved in the development of various types of memory solutions, including EEPROM, SRAM, mask ROM, and NAND. In particular, he was responsible for developing the industry’s first 32Gb CTF NAND in 2007, which now serves as the backbone of 3D NAND products. With 36 years of experience in memory technology, he has obtained 214 US patents and has published 59 papers in numerous prestigious IEEE conferences including ISSCC, IEDM, Symposium on VLSI Technology and IMW. Prior to becoming General Chairman for IMW (International Memory Workshop) in 2012, he served as a member of the technical and organizing committee for 8 years.

Hongbin Zhu

Charles (Hyun) Ahn

EVP & Head of Solution Development

SK hynix

Charles (Hyun) Ahn, EVP & Head of Solution Development, SK hynix Charles (Hyun) Ahn is the EVP and Head of the Solution Development division at SK hynix, as well as the Head of SSD Engineering at Solidigm, where he leads the development of Client SSDs and collaborates with Datacenter teams. A 24-year veteran of SK hynix, Charles is a seasoned engineer and strategist with a deep expertise in NAND process technology, storage solutions (UFS, client/datacenter SSD), and next-gen memory (CXL, PIM). He also possess a comprehensive perspective in directing business strategies, investment decisions, and startup M&A activities for future expansion. He is dedicated to delivering AI-based memory solutions that offer new and enhanced value. Charles earned his PhD from Seoul National University in South Korea.

SK hynix is at the forefront of the industry in NAND technology, substantiating its advancements in NAND bit growth, high performance, and reliability through the industry-leading development, mass production, and evolution of "4D" NAND products. The company's dominance in "4D" NAND technology enables SK hynix to achieve the launch of ultra-high performance UFS 4.0 and datacenter PCIe Gen5 SSD products, that establish its leadership in PCIe Gen5 SSDs for mobile PCs. Ultra-high performing storage I/O supporting massive calculations and high capacity/low-latency storage assisting massive data access are indispensable. We are entering an age of multimodal AI requiring analysis, learning, and inference utilizing Large Language Models (LMM)and multimedia data across edge, core and cloud infrastructures spanning datacenters, PCs, smartphones, and even autonomous vehicles (AV). SK hynix aims to achieve these technological advancements of storage by dominating the technology innovation for the next-generation datacenter, PCIe Gen6 SSDs and UFS 5.0 memory based products.

Keynote 4: Solidigm
"Density Rules" for Storage
from the Core to the Edge

Tuesday, August 8th, 1:40pm

Jihyo Lee

Robert Frickey

Fellow at Solidigm


Robert Frickey is a Fellow at Solidigm, where he is responsible for data center SSD product development. Prior to Solidigm, he spent 21 years at Intel successfully developing multiple generations of SSDs as well as NOR and NAND flash memory components. He has published several peer-reviewed journal papers and holds 10 patents. He earned his B.S .in electrical engineering from Princeton University.

Compute and storage are becoming increasingly decentralized, driven by exponential growth in IoT, rapid 5G adoption, and the need to manage costs while increasing agility. Storage challenges in the core data center are even more acute at the regional edge and further out with on-prem deployments. Space, power, cooling and serviceability are all important considerations. Join Solidigm to hear about today’ shifting storage landscape and how QLC technology -- with its combination of dense, performant and affordable storage -- is well-positioned to rule from the core to the edge.

Keynote 5: FADU
Gen 5 SSDs Unleash Performance
and Sustainability in the Datacenter

Tuesday, August 8th, 2:10 pm


Jihyo Lee

Co-Founder & CEO


Jihyo Lee is CEO and co-founder of FADU Inc. He is a former partner at Bain & Company, and an extraordinarily successful serial entrepreneur involved in multiple businesses in technology, telecom, and energy. As CEO, he has established FADU as a fabless semiconductor innovator, uniting exceptional industry talent to create a revolution in data center and storage for next-generation computing architectures. Jihyo holds a B.S and M.S degree in Engineering from Seoul National University and an MBA from The Wharton School University of Pennsylvania.


Ross Stenfort

Hardware Storage Engineer


Ross Stenfort is a prominent member of Meta’s Storage Hardware team. He has over 20 years of experience developing and bringing leading edge storage products to the market. Ross works closely with industry partners and standards organizations including NVM Express, SNIA/EDSFF, and Open Compute Project (OCP) to innovate on and promote industry leading initiatives. With experience including ASIC design, he has an appreciation for the challenges facing SSD providers with delivering performance and QoS within a shrinking power envelope. Ross is an inventor and author of over 40 patents. Ross holds an Electrical Engineering degree from California Polytechnic State University- San Luis Obispo.

Join FADU’s CEO, Jihyo Lee, in conversation with Ross Stenfort, Hardware Storage Engineer at Meta. These two storage experts will discuss the advent of the next generation SSDs into the data center elaborating on key innovations to improve sustainability in the datacenter with power improvements and improvements with write amplification in the data center. Ross will share his solutions proposed in the industry, through industry-wide efforts such as Flexible Data Placement to mitigate these issues. Jihyo will address the architectural solutions in controllers to mitigate these issues.

Keynote 6: Microchip
Top 3 Challenges and Solutions for
Delivering the Full Premise of CXL™

Tuesday, August 8th, 2:40 pm


Samer Haija

Director of Marketing, Data Center Solutions, Microchip Technology, Inc.

Microchip Technology

Samer Haija manages a team of product managers, strategic planners, and customer marketing managers responsible for setting and executing the product strategy to deliver sustainable growth for Microchip’s Data Center Solutions business unit. Haija has Bachelor of Science degrees in both Aerospace Engineering as well as Electrical and Computer Engineering. Samer is passionate about building better solutions, not just to create products but also to grow organizations, strengthen teams and achieve improved customer experiences.

Compute Express Link™ (CXL™) is a new technology that allows for faster data transfer between processors and other components, making it ideal for high-performance computing such as Artificial Intelligence (AI), Machine Learning (ML), Advanced Driver Assisted Systems (ADAS) and other computational workload applications. Despite its benefits, many organizations may face challenges in deploying CXL solutions. We will explore the top three challenges that organizations are likely to encounter and address strategies for successfully deploying CXL solutions to improve performance and efficiency. Challenges include: • Compatibility issues with existing hardware • Need for specialized expertise to implement CXL solutions • High cost of upgrading to CXL-compatible technology Attendees will gain a deeper understanding of the potential benefits and challenges of CXL deployment, as well as practical insights into how to navigate these challenges and realize the full potential of this cutting-edge technology. Microchip is a key contributor to the CXL Consortium, both as a CXL board member and participant in the technical working groups developing the CXL specification. Microchip’s portfolio encompasses the essential ingredients for data centers, including storage, embedded controllers, wired and wireless connectivity, security, timing, memory, power and analog to create a total system solution. This portfolio of technologies can be tailored to your unique security, platform, performance and business requirements to simplify your development and speed your time to market.

Keynote 7: Marvell
Transforming Cloud Infrastructure for the AI Era

Wednesday, August 9th, 11:00 am

Gary Kotzur

Nigel Alvares

Vice President of Global Marketing and Business Planning

Marvell Technology Inc

Nigel Alvares is Vice President of Global Marketing and Business Planning at Marvell Technology. He is responsible for leading Marvell's corporate marketing, portfolio marketing, industry analyst relations, market research, end market strategic planning, demand planning, and pricing for the company. Nigel joined Marvell in 2017 as Vice President of Marketing for its Flash Business Unit, where he led its general management covering product management, product marketing, business strategy, product roadmaps, customer relationships and design wins with profit and loss (P&L) responsibilities. Before joining Marvell, Nigel worked for Inphi, a high-speed interconnect innovator, where he helped launch industry-first non-volatile memory controller chipsets for emerging NVDIMMs. He was also responsible for managing marketing and business development with cloud data center, server OEM and DRAM memory maker customer relationships for the DDR memory interconnect business unit. Prior to Inphi, Nigel was a founding member of PMC-Sierra’s Enterprise Storage Division and helped build it into the company’s largest revenue generating business unit, managing its widely-deployed storage controller and disk interconnect products from inception. Nigel possesses over 20 years of data infrastructure semiconductor product management and marketing experience spanning data networking, storage, memory, and server compute. He earned a Bachelor of Electrical Engineering (BEE) degree from McGill University (Montreal, Canada) and an MBA from Simon Fraser University (Vancouver, Canada).

Over the past year, ChatGPT and other generative artificial intelligence (AI) applications have taken the world by storm with unprecedented adoption rates, enabled by cloud infrastructure. These generative AI applications are rapidly advancing with larger, more complex, and diverse data sets, putting significant pressure on cloud data center infrastructure to support these changes. Scaling traditional compute capabilities alone is not going to be enough to meet AI requirements. Further compounding the challenge is the reality that every cloud is unique with its own requirements and purpose, making a one-size-fits-all approach unfeasible. A more holistic and transformative approach is needed that integrates software, memory, storage, networking, optical interconnectivity and more. In this keynote, Marvell’s Nigel Alvares discusses the cloud evolution and introduces emerging cloud-optimized silicon architecture solutions covering storage and memory that will help AI to continue to scale.

SuperWomen in Flash Leadership Award

Keynote 8: NEO Semiconductor
New Architectures which will Drive Future
NAND and DRAM Solutions

Wednesday, August 9th, 11:40am


Andy Hsu


NEO Semiconductor

Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company’s growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master’s degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor’s degree from the National Cheng-Kung University in Taiwan.

DRAM and NAND flash memory are two of the most important types of memory in computer and electronic systems. In the past 30 years, DRAM cell size has shrunk many times to scale density from megabits to gigabits. However, scaling slowed when the technology node reached 14 nm around 2019. As for NAND flash, latency significantly increases with each generation (e.g., 50% worse for QLC vs. TLC). This limits system performance. NEO Semiconductor™ proposes two innovative technologies - 3D X-DRAM™ and X-NAND™ - to overcome these challenges. A new DRAM structure, leveraging 3D design, is urgently needed to overcome scaling issues. This new structure, called 3D X-DRAM, implements many new 3D processes and uses new methods to overcome process yield issues. Additionally, a new NAND structure, leveraging 3D design, is needed to further address performance challenges. The innovation of X-NAND improves latency by increasing parallelism with more planes and utilizing new techniques for reading multiple bits in one cycle, to achieve increasing sequential throughput by 20X. New 3D architectures have the potential to enable the next wave of memory and storage solutions.

Keynote 9: Silicon Motion
SSD Controller Innovations for PC,
Automotive and Enterprise

Wednesday, August 9th, 1:10 pm

Pete Hazen

Robert Fan

President of Silicon Motion, Inc., USA

Silicon Motion

Robert Fan, President of Silicon Motion, Inc. USA Robert Fan has served as President of Silicon Motion, Inc. USA in charge of business operations in the Americas and Europe. He also oversees corporate marketing communications, public relations, and graphics product line. Robert has over 25 years of sales and marketing experience and joined Silicon Motion in May 2013. Prior to Silicon Motion, Mr. Fan served in executive management roles at Spansion, IDT, Staktek, and at two venture capital backed startups. He also spent over nine years at Intel in sales, marketing and management positions and was a chip designer earlier in his career. Robert earned a BS and MS in Electrical Engineering and Computer Science (EECS) from University of California Berkeley and Santa Clara University respectively.

NAND Controllers are the hearts and brains of SSDs. As storage platforms and NAND technologies evolve, SSD vendors need to deliver innovations in order to meet the performance, power, features, and cost requirements of customers. Additionally, these storage solutions need to align with the latest interface standards and the latest NAND TLC/QLC technologies. Silicon Motion, as a leading merchant supplier of SSD controllers and solutions, will discuss the current and future SSD controller innovations that can address the evolving and unique requirements in PC, Automotive and Enterprise markets – including a "walk through" of how their SSD Development Platforms are supporting unprecedented new levels of virtualization, security threat prevention, and high-performance applications.

Keynote 10: Western Digital
Advancing Composable Infrastructure
with NVMe over Fabric

Wednesday, August 9th, 1:40 pm


Barrett Edwards

CTO Platform Business Unit

Western Digital

Barrett Edwards is the CTO of the Platforms Business Unit at Western Digital. His responsibilities include defining the technical roadmap and strategy of storage platform products, building partner relationships, and solution development activities. Previously he held development management and product planning responsibilities at SanDisk and Fusion-io for PCIe storage products as well as software defined network appliances. Barrett earned Bachelor of Science and Master of Science degrees in Electrical and Computer Engineering and a Master of Business Administration degree from Brigham Young University.

Local PCIe attached flash storage has transformed data center computing architectures over the past decade. NVMe™ is now the undisputed standard for SSDs and has brought many benefits in deployment reliability, multi-generational consistency, and management integration. In this keynote, Western Digital will discuss how NVMe-oF™ attached storage offers the ability to improve asset utilization without sacrificing the native performance characteristics offered by locally attached devices. As computing architectures continue to evolve, multi-system integration and resource coordination provide a path to increase application efficiency for the next decade.

 Wednesday, August 9th, 2:10 pm

Richelle Ahlvers

Trends in Storage and Data: New Directions for Industry Standards

With a rapidly changing environment and an increasing variety of options, managing both data and storage systems is an increasingly complex proposition. Richelle Ahlvers, SNIA Vice Chair, will look at some of the key recent and emerging technologies. She will also talk about how SNIA is adapting to work across increasingly data-centric technologies, and talk about how SNIA is not only working to deliver education and new standards, but partnering with other industry consortiums, and open communities to work together to accelerate adoption of these new technologies.

Keynote 11: Western Digital
Reinvigorating Virtuous Cycle
of Growth for NAND Flash

Wednesday, August 9th, 2:20 pm

Debendra Das Sharma

Alper Ilkbahar

Senior VP of Technology and Strategy

Western Digital

Alper Ilkbahar is Sr VP Technology & Strategy overseeing development of NAND technology development, next generation technologies and corporate research functions at Western Digital. A veteran of the semiconductor and storage industries, Alper rejoined Western Digital in 2022 from Intel Corp, where he was VP of Data Center Group and GM of the Intel Optane Group, overseeing development of memory and storage solutions. Previously, he held various executive and management roles at SanDisk’s memory and Intel’s microprocessor divisions. Alper earned a bachelor’s degree in electrical engineering from Boğazici University in Istanbul, Turkey, a master’s degree in electrical engineering from the University of Michigan, and an MBA degree from the Wharton School of the University of Pennsylvania. He holds more than 50 patents in the fields of semiconductor process, device, design and testing and has published multiple conference and journal papers in his areas of expertise.

NAND Flash industry has enjoyed a virtuous cycle of growth for decades where each successive technology node reduced bit cost, which in turn enabled new applications and increased demand that made investments possible to develop next generation technology nodes and increase bit output. As the maturing semiconductor industry struggled with scaling challenges, NAND Flash innovated by scaling in the 3rd dimension and continued its bit growth trajectory. However, as we are moving into a mature era of 3D, scaling by only increasing layer count results in a sub-linear cost reduction while producing higher bit growth. This breaks the aforementioned virtuous cycle of growth, producing more bits than the market can absorb given cost reductions and challenges the affordability of future investments. NAND scaling needs to move away from solely increasing layer count and look for new avenues for cost and complexity reduction. Equipment productivity improvements and reduction in consumables remain critical focus for the supply chain to contribute to the cost reduction. Ultimately, the health of the storage industry will be determined by creating value and new applications through innovation for our customers and by generating new demand. Without this, we will be unable to invest capital in new R&D and technological advances. In this talk we will cover the price elasticity of demand for NAND Flash that governs the supply-demand relationship in the market; discuss the increasing capital intensity of scaling 3D NAND and its cost implications; and finally demonstrate some of the breakthrough innovations in our latest generation of 3D NAND technology to tackle cost and performance scaling challenges.




Conference ConCepts