2023 Keynotes Profiles and Abstracts

Robert Frickey

Fellow at Solidigm

Solidigm

Robert Frickey is a Fellow at Solidigm, where he is responsible for data center SSD product development. Prior to Solidigm, he spent 21 years at Intel successfully developing multiple generations of SSDs as well as NOR and NAND flash memory components. He has published several peer-reviewed journal papers and holds 10 patents. He earned his B.S .in electrical engineering from Princeton University.

Abstract:
Join FADU’s CEO, Jihyo Lee, in conversation with Ross Stenfort, Hardware Storage Engineer at Meta. These two storage experts will discuss the advent of the next generation SSDs into the data center elaborating on key innovations to improve sustainability in the datacenter with power improvements and improvements with write amplification in the data center. Ross will share his solutions proposed in the industry, through industry-wide efforts such as Flexible Data Placement to mitigate these issues. Jihyo will address the architectural solutions in controllers to mitigate these issues.

Samer Haija

Director of Marketing, Data Center Solutions, Microchip Technology, Inc.

Microchip Technology

Samer Haija manages a team of product managers, strategic planners, and customer marketing managers responsible for setting and executing the product strategy to deliver sustainable growth for Microchip’s Data Center Solutions business unit. Haija has Bachelor of Science degrees in both Aerospace Engineering as well as Electrical and Computer Engineering. Samer is passionate about building better solutions, not just to create products but also to grow organizations, strengthen teams and achieve improved customer experiences.

Abstract:
Compute Express Link™ (CXL™) is a new technology that allows for faster data transfer between processors and other components, making it ideal for high-performance computing such as Artificial Intelligence (AI), Machine Learning (ML), Advanced Driver Assisted Systems (ADAS) and other computational workload applications. Despite its benefits, many organizations may face challenges in deploying CXL solutions. We will explore the top three challenges that organizations are likely to encounter and address strategies for successfully deploying CXL solutions to improve performance and efficiency. Challenges include: • Compatibility issues with existing hardware • Need for specialized expertise to implement CXL solutions • High cost of upgrading to CXL-compatible technology Attendees will gain a deeper understanding of the potential benefits and challenges of CXL deployment, as well as practical insights into how to navigate these challenges and realize the full potential of this cutting-edge technology. Microchip is a key contributor to the CXL Consortium, both as a CXL board member and participant in the technical working groups developing the CXL specification. Microchip’s portfolio encompasses the essential ingredients for data centers, including storage, embedded controllers, wired and wireless connectivity, security, timing, memory, power and analog to create a total system solution. This portfolio of technologies can be tailored to your unique security, platform, performance and business requirements to simplify your development and speed your time to market.

Nigel Alvares

Vice President of Global Marketing and Business Planning

Marvell Technology Inc

Nigel Alvares is Vice President of Global Marketing and Business Planning at Marvell Technology. He is responsible for leading Marvell's corporate marketing, portfolio marketing, industry analyst relations, market research, end market strategic planning, demand planning, and pricing for the company. Nigel joined Marvell in 2017 as Vice President of Marketing for its Flash Business Unit, where he led its general management covering product management, product marketing, business strategy, product roadmaps, customer relationships and design wins with profit and loss (P&L) responsibilities. Before joining Marvell, Nigel worked for Inphi, a high-speed interconnect innovator, where he helped launch industry-first non-volatile memory controller chipsets for emerging NVDIMMs. He was also responsible for managing marketing and business development with cloud data center, server OEM and DRAM memory maker customer relationships for the DDR memory interconnect business unit. Prior to Inphi, Nigel was a founding member of PMC-Sierra’s Enterprise Storage Division and helped build it into the company’s largest revenue generating business unit, managing its widely-deployed storage controller and disk interconnect products from inception. Nigel possesses over 20 years of data infrastructure semiconductor product management and marketing experience spanning data networking, storage, memory, and server compute. He earned a Bachelor of Electrical Engineering (BEE) degree from McGill University (Montreal, Canada) and an MBA from Simon Fraser University (Vancouver, Canada).

Abstract:
Over the past year, ChatGPT and other generative artificial intelligence (AI) applications have taken the world by storm with unprecedented adoption rates, enabled by cloud infrastructure. These generative AI applications are rapidly advancing with larger, more complex, and diverse data sets, putting significant pressure on cloud data center infrastructure to support these changes. Scaling traditional compute capabilities alone is not going to be enough to meet AI requirements. Further compounding the challenge is the reality that every cloud is unique with its own requirements and purpose, making a one-size-fits-all approach unfeasible. A more holistic and transformative approach is needed that integrates software, memory, storage, networking, optical interconnectivity and more. In this keynote, Marvell’s Nigel Alvares discusses the cloud evolution and introduces emerging cloud-optimized silicon architecture solutions covering storage and memory that will help AI to continue to scale.

Andy Hsu

CEO

NEO Semiconductor

Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company’s growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master’s degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor’s degree from the National Cheng-Kung University in Taiwan.

Abstract:
DRAM and NAND flash memory are two of the most important types of memory in computer and electronic systems. In the past 30 years, DRAM cell size has shrunk many times to scale density from megabits to gigabits. However, scaling slowed when the technology node reached 14 nm around 2019. As for NAND flash, latency significantly increases with each generation (e.g., 50% worse for QLC vs. TLC). This limits system performance. NEO Semiconductor™ proposes two innovative technologies - 3D X-DRAM™ and X-NAND™ - to overcome these challenges. A new DRAM structure, leveraging 3D design, is urgently needed to overcome scaling issues. This new structure, called 3D X-DRAM, implements many new 3D processes and uses new methods to overcome process yield issues. Additionally, a new NAND structure, leveraging 3D design, is needed to further address performance challenges. The innovation of X-NAND improves latency by increasing parallelism with more planes and utilizing new techniques for reading multiple bits in one cycle, to achieve increasing sequential throughput by 20X. New 3D architectures have the potential to enable the next wave of memory and storage solutions.

Robert Fan

President of Silicon Motion, Inc., USA

Silicon Motion

Robert Fan, President of Silicon Motion, Inc. USA Robert Fan has served as President of Silicon Motion, Inc. USA in charge of business operations in the Americas and Europe. He also oversees corporate marketing communications, public relations, and graphics product line. Robert has over 25 years of sales and marketing experience and joined Silicon Motion in May 2013. Prior to Silicon Motion, Mr. Fan served in executive management roles at Spansion, IDT, Staktek, and at two venture capital backed startups. He also spent over nine years at Intel in sales, marketing and management positions and was a chip designer earlier in his career. Robert earned a BS and MS in Electrical Engineering and Computer Science (EECS) from University of California Berkeley and Santa Clara University respectively.

Abstract:
NAND Controllers are the hearts and brains of SSDs. As storage platforms and NAND technologies evolve, SSD vendors need to deliver innovations in order to meet the performance, power, features, and cost requirements of customers. Additionally, these storage solutions need to align with the latest interface standards and the latest NAND TLC/QLC technologies. Silicon Motion, as a leading merchant supplier of SSD controllers and solutions, will discuss the current and future SSD controller innovations that can address the evolving and unique requirements in PC, Automotive and Enterprise markets – including a "walk through" of how their SSD Development Platforms are supporting unprecedented new levels of virtualization, security threat prevention, and high-performance applications.

Barrett Edwards

CTO Platform Business Unit

Western Digital

Barrett Edwards is the CTO of the Platforms Business Unit at Western Digital. His responsibilities include defining the technical roadmap and strategy of storage platform products, building partner relationships, and solution development activities. Previously he held development management and product planning responsibilities at SanDisk and Fusion-io for PCIe storage products as well as software defined network appliances. Barrett earned Bachelor of Science and Master of Science degrees in Electrical and Computer Engineering and a Master of Business Administration degree from Brigham Young University.

Abstract:
Local PCIe attached flash storage has transformed data center computing architectures over the past decade. NVMe™ is now the undisputed standard for SSDs and has brought many benefits in deployment reliability, multi-generational consistency, and management integration. In this keynote, Western Digital will discuss how NVMe-oF™ attached storage offers the ability to improve asset utilization without sacrificing the native performance characteristics offered by locally attached devices. As computing architectures continue to evolve, multi-system integration and resource coordination provide a path to increase application efficiency for the next decade.

Alper Ilkbahar

Senior VP of Technology and Strategy

Western Digital

Alper Ilkbahar is Sr VP Technology & Strategy overseeing development of NAND technology development, next generation technologies and corporate research functions at Western Digital. A veteran of the semiconductor and storage industries, Alper rejoined Western Digital in 2022 from Intel Corp, where he was VP of Data Center Group and GM of the Intel Optane Group, overseeing development of memory and storage solutions. Previously, he held various executive and management roles at SanDisk’s memory and Intel’s microprocessor divisions. Alper earned a bachelor’s degree in electrical engineering from Boğazici University in Istanbul, Turkey, a master’s degree in electrical engineering from the University of Michigan, and an MBA degree from the Wharton School of the University of Pennsylvania. He holds more than 50 patents in the fields of semiconductor process, device, design and testing and has published multiple conference and journal papers in his areas of expertise.

Abstract:
NAND Flash industry has enjoyed a virtuous cycle of growth for decades where each successive technology node reduced bit cost, which in turn enabled new applications and increased demand that made investments possible to develop next generation technology nodes and increase bit output. As the maturing semiconductor industry struggled with scaling challenges, NAND Flash innovated by scaling in the 3rd dimension and continued its bit growth trajectory. However, as we are moving into a mature era of 3D, scaling by only increasing layer count results in a sub-linear cost reduction while producing higher bit growth. This breaks the aforementioned virtuous cycle of growth, producing more bits than the market can absorb given cost reductions and challenges the affordability of future investments. NAND scaling needs to move away from solely increasing layer count and look for new avenues for cost and complexity reduction. Equipment productivity improvements and reduction in consumables remain critical focus for the supply chain to contribute to the cost reduction. Ultimately, the health of the storage industry will be determined by creating value and new applications through innovation for our customers and by generating new demand. Without this, we will be unable to invest capital in new R&D and technological advances. In this talk we will cover the price elasticity of demand for NAND Flash that governs the supply-demand relationship in the market; discuss the increasing capital intensity of scaling 3D NAND and its cost implications; and finally demonstrate some of the breakthrough innovations in our latest generation of 3D NAND technology to tackle cost and performance scaling challenges.